This invention relates to the fabrication of a long-memory-retention-time single transistor ferroelectric RAM, and specifically to a ferroelectric RAM having a ferroelectric element which is encapsulated in a high-k dielectric.
Prior art single transistor metal-ferroelectric-oxide semiconductor (MFOS) gate stacks include a top electrode, a ferroelectric layer and an oxide layer. After such a device is programmed, electrons, or holes, may flow from the top electrode into and become trapped in the ferroelectric layer. The polarity of the trapped charge is opposite to that of the polarization charges. Therefore, these trapped charges cause the reduction of the memory window.
A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack.
A method of forming a ferroelectric memory transistor includes preparing a substrate, including forming active regions and an oxide device isolation region; depositing a gate oxide layer; depositing a gate placeholder layer; masking and removing a portion of the gate placeholder layer and the gate oxide layer to form a gate placeholder structure in a gate region; depositing a layer of oxide over the structure to a depth of approximately twice that of the gate placeholder layer; smoothing the structure to the level of the gate placeholder layer; removing the gate placeholder structure and the gate oxide layer in the gate region, forming a gate void in the gate region; depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup; filling the high-k cup with a ferroelectric material to form a ferroelectric element; smoothing the structure to the upper level of the ferroelectric element; depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap over the ferroelectric element; depositing a top electrode over the high-k cap to form a gate electrode and gate stack; depositing a layer of passivation oxide over the structure; etching the passivation oxide to from contact vias to the active regions and the gate stack; and metallizing the structure to complete the ferroelectric memory transistor.
It is an object of the invention to provide a non-volatile ferroelectric memory device, which eliminates the leakage-related transistor memory retention degradation.
Another object of the invention is to provide a ferroelectric memory cell wherein the ferroelectric element is encapsulated in a high-k dielectric.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.